The present invention relates to very large scale integration (VLSI) design, and more specifically, to placement clustering-based white space reservation.
A VLSI design is typically subdivided into hierarchical components that can be designed concurrently. For example, a chip is divided into a number of units, and a number of macros, which can be referred to as large blocks, make up each unit of the chip. The design cycle includes several phases from the logic design to the physical implementation of a chip. For example, in the high-level design phase, synthesis is a process by which desired functionality is mapped to logic gates. In floorplanning, areas of the chip are designated for different components. As the logic density of chips increases, the size and aspect ratio of each large block also increases. As a result, the large blocks dominate the area defining the unit, leaving little or no room between macros for the latches and buffers that address unit level constraints.